54C164245 datasheet(14/23 Pages) STMICROELECTRONICS

14 / 23 page

Electrical characteristics

54AC164245

14/23

DocID18093 Rev 4

tPZL (1)

Propagation delay time,

output enable, DIRn to bus

(active low), CL = 50 pF

Port A = 3.3 V

Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 2.7 to 3.3 V

1.0

Propagation delay time,

output enable, DIRn to bus

(active low), CL= 50 pF

Port A = Port B = 3.3 V

VDD1 = 2.7 to 3.3 V

VDD2 = 2.7 to 3.3 V

Port A = Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 4.5 to 5.5 V

tPZH (1)

Propagation delay time,

output enable, DIRn to bus

(active high), CL = 50 pF

Port A = 3.3 V

Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 2.7 to 3.3 V

Propagation delay time,

output enable, DIRn to bus

(active high), CL= 50 pF

Port A = Port B = 3.3 V

VDD1 = 2.7 to 3.3 V

VDD2 = 2.7 to 3.3 V

Port A = Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 4.5 to 5.5 V

tPLZ (1)

Propagation delay time,

output disable, DIRn to bus

(low impedance), CL =50 pF

Port A = 3.3 V

Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 2.7 to 3.3 V

Propagation delay time,

output disable, DIRn to bus

(low impedance), CL= 50 pF

Port A = Port B = 3.3 V

VDD1 = 2.7 to 3.3 V

VDD2 = 2.7 to 3.3 V

Port A = Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 4.5 to 5.5 V

tPHZ (1)

Propagation delay time,

output disable, DIRn to bus

(high impedance), CL = 50 pF

Port A = 3.3 V

Port B = 5.0 V

VDD1 = 4.5 to 5.5 V

VDD2 = 2.7 to 3.3 V

Propagation delay time,

output disable, DIRn to bus

(high impedance), CL= 50 pF

Port A = Port B = 3.3 V

VDD1 = 2.7 to 3.3 V

VDD2 = 2.7 to 3.3 V

Port A = Port B = 5 V

VDD1 = 4.5 to 5.5 V

VDD2 = 4.5 to 5.5 V

Table 7. AC electrical characteristics (continued)

Symbol

Parameter

Port voltage

Test condition (VDD)

Limits

Unit

Min. Max.

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