DS75 datasheet(13/13 Pages) DALLAS

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DS75

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NOTES:

1. All voltages are referenced to ground.

2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.

3. IDD specified with O.S. pin open.

4. IDD specified with VDD at 5.0V and SDA, SCL = 5.0V, 0

°C to 70°C.

5. After this period, the first clock pulse is generated.

6. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

7. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT

≤ 250 ns must

then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tRMAX +tSU:DAT = 1000+250 = 1250 ns before the SCL line is released.

8. Cb – total capacitance of one bus line in pF.

Internal heating caused by O.S. loading will cause the DS75 to read approximately 0.5

°C higher if

O.S. is sinking the max rated current.

TIMING DIAGRAMS Figure 6

DS75 bảng dữ liệu(PDF) 13 Page - Dallas Semiconductor