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NOTES:

1. All voltages are referenced to ground.

may not reproduce the correct memory contents. Therefore, under low voltage conditions, it is

recommended to set either the most significant bit or all five most significant bits of TA2 to 1.

Internal circuitry of the chip will force these five bits back to 0 before they are shifted in the address

counter and CRC generator.

3. Input load is to ground.

4. An additional reset or communication sequence cannot begin until the reset high time has expired.

5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is

guaranteed to be valid within 1

µs of this falling edge and will remain valid for 14 µs minimum. (15

µs total from falling edge on 1-Wire bus.)

7. 30 nanocoulombs per 72 time slots @ 5.0V.

Ω pullup to V

µs.

9. Capacitance on the data pin could be 800 pF when power is first applied. If a 5k

Ω resistor is used to

µs after power has been applied the parasite capacitance will not affect

normal communications.

guarantee a presence pulse.