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DS1867 bảng dữ liệu(PDF) 7 Page - Dallas Semiconductor |
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DS1867 bảng dữ liệu(HTML) 7 Page - Dallas Semiconductor |
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7 / 14 page ![]() DS1867 7 of 14 102199 POWER-DOWN EEPROM TIMING REQUIREMENTS Figure 6 TYPICAL APPLICATION CONFIGURATIONS Figures 7 and 8 show two typical application configurations for the DS1867. By connecting the wiper terminal of the part to a high impedance load, the effects of the wiper resistance is minimized, since the wiper resistance can vary from 400 to 1000 ohms depending on wiper voltage. Figure 7 presents the device connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by the following equation: Av = -n/(255-n); where n = 0 to 255 Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper resistance to minimize its effect on circuit gain. INVERTING VARIABLE GAIN AMPLIFIER Figure 7 DS1867 |
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