ICS810251 datasheet(9/15 Pages) IDT

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ICS810251I Data Sheet

VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR

ICS810251AGI REVISION B OCTOBER 5, 2012

Schematic Example

Figure 1 shows an example of the 810251I application schematic. In

this example, the device is operated either at VDD = 3.3V or 2.5V. The

decoupling capacitors should be located as close as possible to the

power pin. The input is driven by an LVCMOS driver. An optional

3-pole filter can also be used for additional spur reduction. It is

recommended that the loop filter components be laid out for the

3-pole option. This will also allow the 2-pole filter to be used.

Figure 1. P.C. ICS810251I Schematic Example

0.001 uF

LF1

RD1

Not Install

RU1

Logic Control Input Examples

VDD

TBD

To Logic

Input

pins

Zo = 50

TBD

Set Logic

Input to

'1'

TBD

LF0

VDD

VDDO

VDD

C30

0.01u

LVCMOS_Receiv er

TBD

VDD

LVCMOS_Driv er

XTAL_IN

0.1u

Set Logic

Input to

'0'

SPARE

XTAL_OUT

To Logic

Input

pins

SPARE

PLL_SEL

GND

Reserv ed

VDDO

VDDA

VDD

GND

XTAL_OUT

XTAL_IN

GND

LF0

LF1

VDD

CLK_IN

0.1u

3-pole loop filter example - (optional)

TBD

10uF

0.1u

VDDA

VDD

VDD=VDDO=3.3V

RD2

Zo = 50

C45

10u

RU2

Not Install

2-pole loop filter

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