DS1609

020499 2/7

OPERATION – READ CYCLE

The main elements of the dual port RAM are shown in

Figure 1.

A read cycle to either port begins by placing an address

on the multiplexed bus pins AD0 – AD7. The port enable

control (CE) is then transitioned low. This control signal

causes address to be latched internally. Addresses can

be removed from the bus provided address hold time is

met. Next, the output enable control (OE) is transitioned

low, which begins the data access portion of the read

cycle. With both CE and OE active low, data will appear

remain valid as long as both port enable and output en-

able remains low. A read cycle is terminated with the

first occurring rising edge of either CE or OE. The ad-

dress/data bus will return to a high impedance state af-

rising edge. WE must remain high during read cycles.

OPERATION – WRITE CYCLE

A write cycle to either port begins by placing an address

on the multiplexed bus pins AD0 – AD7. The port enable

control (CE) is then transitioned low. This control signal

causes address to be latched internally. As with a read

cycle, the address can be removed from the bus pro-

vided address hold time is met. Next the write enable

control signal (WE) is transitioned low which begins the

write data portion of the write cycle. With both CE and

WE active low the data to be written to the selected

memory location is placed on the multiplexed bus. Pro-

met, data is written into the memory and the write cycle

is terminated on the first occurring rising edge of either

CE or WE. Data can be removed from the bus as soon

as the write cycle is terminated. OE must remain high

during write cycles.

ARBITRATION

The DS1609 dual port RAM has a special cell design

that allows for simultaneous accesses from two ports

(see Figure 2). Because of this cell design, no arbitra-

tion is required for read cycles occurring at the same in-

stant. However, an argument for arbitration can be

made for reading and writing the cell at the exact same

instant or for writing from both ports at the same instant.

A simple way to assure that read/write conflicts don’t oc-

cur is to perform redundant read cycles. Write/write ar-

bitration needs can be avoided by assigning groups of

addresses for write operation to one port only. Groups

of data can be assigned check sum bytes which would

guarantee correct transmission. A software arbitration

system using a “mail box” to pass status information can

also be employed.

Each port could be assigned a

unique byte for writing status information which the oth-

er port would read. The status information could tell the

reading port if any activity is in progress and indicate

when activity is going to occur.