DS1307Z datasheet(9/11 Pages) DALLAS

9 / 11 page

DS1307

9 of 11

AC ELECTRICAL CHARACTERISTICS

°C to 70°C or -40°C to +85°C; V

CC =4.5V to 5.5V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

SCL Clock Frequency

fSCL

100

kHz

Bus Free Time Between a STOP and

START Condition

tBUF

4.7

µs

Hold Time (Repeated) START Condition

tHD:STA

4.0

µs

LOW Period of SCL Clock

tLOW

4.7

µs

HIGH Period of SCL Clock

tHIGH

4.0

µs

Set-up Time for a Repeated START

Condition

tSU:STA

4.7

µs

Data Hold Time

tHD:DAT

µs

6, 7

Data Set-up Time

tSU:DAT

250

Rise Time of Both SDA and SCL Signals

1000

Fall Time of Both SDA and SCL Signals

300

Set-up Time for STOP Condition

tSU:STO

4.7

µs

Capacitive Load for each Bus Line

400

I/O Capacitance

CI/O

Crystal Specified Load Capacitance

12.5

NOTES:

All voltages are referenced to ground.

Logic zero voltages are specified at a sink current of 5 mA at VCC=4.5V, VOL=GND for capacitive

loads.

ICCS specified with VCC=5.0V and SDA, SCL=5.0V.

VCC=0V, VBAT=3V.

After this period, the first clock pulse is generated.

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.

The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

CB - total capacitance of one bus line in pF.

ICCA - SCL clocking at max frequency = 100 kHz.

10. SCL only.

11. SDA and SQW/OUT

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