DS1225AB datasheet(2/10 Pages) DALLAS

2 / 10 page

DS1225AB/AD

2 of 10

READ MODE

The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and

CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13

address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be

available to the eight data output drivers within tACC (Access Time) after the last address input signal is

stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not

satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is

either tCO for CE or tOE for OE rather than address access.

WRITE MODE

The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active

(low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the

start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address

inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum

recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive

(high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and

OE active) then WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by

4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and write

protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.

The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs

automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-

impedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium

energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,

the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.

Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1225AB and 4.5 volts for the

DS1225AD.

FRESHNESS SEAL

Each DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected,

guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP , the lithium

energy source is enabled for battery backup operation.

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