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10

CPC7582

Rev. 1.0

If presented with a short duration transient such as a

lightning event, the thermal shutdown feature will not

typically activate. But in an extended power cross

transient, the device temperature will rise and the ther-

mal shutdown will activate forcing the switches to an

“all off” state. At this point the current measured at pin

2 (T

device enters thermal shutdown it will remain in the

“all off” state until the temperature of the device drops

below the activation level of the thermal shutdown cir-

cuit. This will return the device to the state prior to

thermal shutdown. If the transient has not passed,

current will flow at the value allowed by the dynamic

DC current limiting of the switches and heating will

begin again, reactivating the thermal shutdown mech-

anism. This cycle of entering and exiting the thermal

shutdown mode will continue as long as the fault con-

dition persists. If the magnitude of the fault condition is

great enough, the external secondary protector could

activate and shunt all current to ground.

The thermal shutdown mechanism of the CPC7582

can be disable by applying +V

External Protection Elements

The CPC7582 requires only one overvoltage second-

ary protector on the loop side of the device. The inte-

grated protection feature described above negates the

need for protection on the line side. The purpose of

the secondary protector is to limit voltage transients to

levels that do not exceed the breakdown voltage or

input-output isolation barrier of the CPC7582. A fold-

back or crowbar type protector is recommended to

minimize stresses on the device.

Consult Clare’s application note, AN-100, “Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interfaces” for equations related

to the specifications of external secondary protectors,

fused resistors and PTCs.

Data Latch

The CPC7582 has an integrated data latch. The latch

operation is controlled by logic level input pin 11

(LATCH). The data input of the latch is pin 10 (IN

and pin 9 (IN

the data latch is an internal node used for state con-

trol. When LATCH control pin is at logic 0, the data

latch is transparent and data control signals flow

directly through to state control. A change in input will

be reflected in a change is switch state. When LATCH

control pin is at logic 1, the data latch is now active

and a change in input control will not affect switch

state. The switches will remain in the position they

were in when the LATCH changed from logic 0 to logic

1 and will not respond to changes in input as long as

the latch is at logic 1. In addition, TSD input is not tied

to the data latch. Therefore, TSD is not affected by

the LATCH input and TSD input will override state

control via pin 10 (IN

LATCH.