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CS5360 bảng dữ liệu(PDF) 14 Page - Cirrus Logic

tên linh kiện CS5360
Giải thích chi tiết về linh kiện  24-Bit Stereo A/D Converter for Digital Audio
PDF  22 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5360 bảng dữ liệu(HTML) 14 Page - Cirrus Logic

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CS5360
14
DS280PP2
4.7
Power-Down
The CS5360 has a power-down mode wherein typ-
ical consumption drops to 1.0 mW. This is initiated
when a loss of clock is detected (either LRCK or
MCLK in Slave Mode or MCLK in Master Mode),
RST is enabled or DIF0 / DIF1 are at a logic 1. The
initialization sequence will begin whenever valid
clocks are restored, RST is disabled and DIF0 /
DIF1 are restored. If the MCLK / LRCK frequency
ratio changes during power-down, the CS5360 will
adapt to these new operating conditions. However,
only the RST method of power-down will include
the Master/Slave decision in the initialization se-
quence.
4.8
Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS5360
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure6 shows the recommended power arrange-
ments with VA+ connected to a clean +5volt sup-
ply. VD+ should be derived from VA+ through a 2
ohm resistor. VD+ should not be used to power ad-
ditional digital circuitry. All mode pins which re-
quire VD+ should be connected to pin 6 of the
CS5360. All mode pins which require DGND
should be connected to pin 5 of the CS5360.
AGND and DGND, Pins 4 and 5, should be con-
nected together at the CS5360. DGND for the
CS5360 should not be confused with the ground for
the digital section of the system. The CS5360
should be positioned over the analog ground plane
near the digital / analog ground plane split. The an-
alog and digital ground planes must be connected
elsewhere in the system. The CS5360 evaluation
board, CDB5360, demonstrates this layout tech-
nique. This technique minimizes digital noise and
insures proper power supply matching and se-
quencing. Decoupling capacitors should be located
as near to the CS5360 as possible.
4.9
Digital Filter
Figures 12-15 show the performance of the digital
filter included in the CS5360. All plots are normal-
ized to Fs. Assuming a sample rate of 48 kHz, the
0.5 frequency point on the plot refers to 24 kHz.
The filter frequency response scales precisely with
the sample rate.



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