CS5181

DS250PP1

13

Figure 11 illustrates the system connection diagram

for the chip. For best performance, each of the

supply pins should be bypassed to the nearest

ground pin on the chip.

The bypass capacitors

should be located as close to the chip as possible. If

the chip is surface mounted the bypass capacitors

should be on the same side of the circuit card as the

chip.

The CS5181 is a high speed component that re-

quires adherence to standard high-frequency print-

ed circuit board layout techniques to maintain

optimum performance. These include the use of

ground and power planes, using low noise power

supplies in conjunction with proper supply decou-

pling, minimizing circuit trace lengths, and physi-

cal separation of digital and analog components

and circuit traces.

It is preferred that any clock oscillator circuitry be

located on a ground plane separate from the digital

plane in order to ensure that digital noise does not

induce clock jitter.

For additional insight, see the CDB5181 evaluation

board for more details. Also refer to Application

Note AN18 which covers layout and design rules

for high resolution data converters.

AGND1

+5 V

+

+

+

~

3.8 V

Fully

Differential

CMV = 2.375 V

pp

+3.3 V

VA1+

VA2+

AGND2

AGND3

VREFOUT

VREFIN

VREF-

VREF+

VREFCAP

AIN+

AIN-

DGND1

VD1+

VD2+

DGND2

PWDN

MODE

RESET

SYNC

MFLAG

MCLK

MCLK

FSO

SCLK

SDO

SCLK

SDO

Control

Logic

Clock

Source

Data

Interface

CS5181

1

28

8

7

18

4

5

3

2

6

26

27

22

21

12

11

25

24

23

10

9

20

19

17

14

13

16

15

The 3.8 V

fully differential input span is set by the converter’s internal voltage reference at 2.375 V.

An input span of 4.0 V

fully differential would result if an external voltage reference of 2.5 V is used.

pp

pp

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

10 µF

10 µF

1 µF

2200 pF

2200 pF

20

Ω

20

Ω

Figure 11. CS5181 System Connection Diagram