CS5180

17

VREF+ — Positive Voltage Reference

Filter capacitor connection for the reference input buffer. The voltage on this pin equals

VREFINX1.6.

VREF- — Negative Voltage Reference

VREF- is connected to AGND.

VREFOUT — Voltage Reference Output

Output pin for the 2.375 volt on-chip reference relative to AGND.

VREFCAP — Reference Bypass

Filter capacitor connection for the internal reference.

Serial Interface I/O Signals

SCLK, SCLK — Serial Interface Clock

Serial Clock Output. A gated serial clock output from the converter at a rate equal to 1/3 the

MCLK clock rate. The SCLK output is a complement of SCLK and helps reduce radiated noise

if the two lines are run adjacent on the PC board layout.

SDO, SDO —SerialDataOut

Serial Data Output. Output pin for 16-bit serial data word. The SDO output is the complement

of SDO and helps to reduce radiated noise if the two lines are run adjacent on the PC board

layout. Output data is output in twos complement format MSB first.

FSO — Frame Sync Output

The Frame Sync Output indicates the beginning of an output word from the SDO pin by falling

to a logic low state. FSO remains low until all 16 bits are clocked out.

Control Pins

RESET — Reset and Calibration

When the RESET pin is pulled to a logic low the converter will perform a reset of its digital

logic. When the level on this pin is brought back to a logic high the chip starts normal

operation, following a two clock cycle delay period. When MODE = 1 the chip goes through

an internal gain and offset calibration routine following this reset sequence.

PWDN — Power Down Mode

A logic 0 on PWDN pin will put the device into a power-down mode.