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CS4610 bảng dữ liệu(PDF) 17 Page - Cirrus Logic |
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CS4610 bảng dữ liệu(HTML) 17 Page - Cirrus Logic |
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17 / 29 page ![]() DS241PP5 17 CS4610/11 CrystalClear™ SoundFusion™ PCI Audio Accelerator Pin Name Direction Functional Description SCLK Input Main timing driver for digital audio link, both edges used internally for tim- ing. Also functions as the source to the PLL for internal clock generation. FSYNC Input Framing signal for digital audio link, high time indicates left channel data and low time indicates right channel data. FSYNC is sampled on the falling edge of the SCLK input. SDOUT Output Primary output port serial data pin. This data is the CS4610 output stream going to the CS423x DACs. SDOUT transitions on the rising edge of the SCLK input. SDIN Input Primary input port serial data pin. This data contains both CS423x ADC data and the CS423x output data. SDIN is sampled on the falling edge of the SCLK input. LRCLK Output Framing signal for external 4333 DACs, high time indicates left channel data and low time indicates right channel data. LRCLK transitions on the falling edge of the SCLK input. SDO2, SDO3 Output Second and third output port serial data pins. These output streams are the expanded output channels beyond the CS423x left / right pair. The serial data on these pins transition on the falling edge of the SCLK input. Note that this is a DIFFERENT SCLK edge than the one for the SDOUT pin. Table 4. Serial Audio Port Signal Summary for CS4610 + CS423x Expanded Output Configuration CS4610 PCI Accelerator CS423x ISA Codec ABITCLK/SCLK ASYNC/FSYNC ASDOUT/SDOUT MIDIIN ASDIN/SDIN SCLK FSYNC SDIN MIDOUT SDOUT 16.9344 MHz PLL/ Clock Gen JAB2/SDO3 JAB1/SDO2 Analog Out Pair 2 Analog Out Pair 3 Analog Out Pair 1 MCLK Surround Left Left Surround Right Right Center Sub 16.9344 JBB1/LRCLK Figure 11. CS4610 + CS423x Expanded 6-Channel Output Configuration |
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