AT25DF161_13 datasheet(9/52 Pages) ETC2

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AT25DF161

Figure 7-2.

Read Array – 0Bh Opcode

Figure 7-3.

Read Array – 03h Opcode

7.2

Dual-Output Read Array

The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially

read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has

been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two

bits of data to be clocked out of the device on every clock cycle rather than just one.

The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO. To

perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must be clocked

into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting

address location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte

must also be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being

output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is always output

on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO pin while bit six of the

same data byte will be output on the SIO pin. During the next clock cycle, bits five and four of the first data byte will be

output on the SO and SIO pins, respectively. The sequence continues with each byte of data being output after every four

clock cycles. When the last byte (1FFFFFh) of the memory array has been read, the device will continue reading back at

the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the

beginning of the array.

SCK

3687H–DFLASH–5/2013

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