công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

CS4360 bảng dữ liệu(PDF) 18 Page - Cirrus Logic

tên linh kiện CS4360
Giải thích chi tiết về linh kiện  24-Bit, 192 kHz 6 Channel D/A Converter?
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4360 bảng dữ liệu(HTML) 18 Page - Cirrus Logic

Back Button CS4360 Datasheet HTML 14Page - Cirrus Logic CS4360 Datasheet HTML 15Page - Cirrus Logic CS4360 Datasheet HTML 16Page - Cirrus Logic CS4360 Datasheet HTML 17Page - Cirrus Logic CS4360 Datasheet HTML 18Page - Cirrus Logic CS4360 Datasheet HTML 19Page - Cirrus Logic CS4360 Datasheet HTML 20Page - Cirrus Logic CS4360 Datasheet HTML 21Page - Cirrus Logic CS4360 Datasheet HTML 22Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 36 page
background image
CS4360
18
DS517PP1
4.5.2
CONTROL PORT ENABLE (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Control Port will become active and reset to the default settings when this function is enabled.
4.5.3
POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.
4.5.4
POPGUARD® TRANSIENT CONTROL (POPG)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PopGuard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
the quiescent voltage during power-on or power-off when this function is enabled. Please see section
6.4 for implementation details.
4.5.5
FREEZE CONTROLS (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the control port registers take effect simulta-
neously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
4.5.6
MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com