CS4340

DS297PP3

15

DIF1 and DIF0

6 & 7 Digital Interface Format (I

nput) - The required relationship between the Left/Right clock, serial

clock and serial data is defined by the Digital Interface Format and the options are detailed in

Figures 16-19

FILT+

9

Positive Voltage Reference (

Output) - Positive reference for internal sampling circuits. An

external capacitor is required from FILT+ to analog ground, as shown in Figure 4. The recom-

mended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz.

FILT+ is not intended to supply external current. FILT+ has a typical source impedance of

250 k

Ω and any current drawn from this pin will alter device performance.

VQ

10

Quiescent Voltage (

Output) - Filter connection for internal quiescent reference voltage, typi-

cally 50% of VA. Capacitors must be connected from VQ to analog ground, as shown in

Figure 4. VQ is not intended to supply external current. VQ has a typical source impedence of

250 k

Ω and any current drawn from this pin will alter device performance.

REF_GND

11

Reference Ground (

Input) - Ground reference for the internal sampling circuits. Must be con-

nected to analog ground.

AOUTR and AOUTL

12 & 15 Analog Outputs (

Output) - The full scale analog output level is specified in the Analog Charac-

teristics specifications table.

AGND

13

Ground (

Input) - Ground Reference.

VA

14

Analog Power (

Input) - Analog power supply. Typically 3 to 5 VDC.

MUTEC

16

Mute Control (

Output) - The Mute Control pin goes high during power-up initialization, reset,

muting, master clock to left/right clock frequency ratio is incorrect or power-down. This pin is

intended to be used as a control for an external mute circuit to prevent the clicks and pops that

can occur in any single supply system. Use of Mute Control is not mandatory but recommended

for designs requiring the absolute minimum in extraneous clicks and pops.

.

DIF1

DIF0

DESCRIPTION

FORMAT

FIGURE

00

0

16

0

1

Left Justified, up to 24-bit data

1

17

1

0

Right Justified, 24-bit Data

2

18

1

1

Right Justified, 16-bit Data

3

19

Table 4. Digital Interface Format - DIF1 and DIF0