CS42L50 datasheet(12/48 Pages) CIRRUS

12 / 48 page

CS42L50

DS544PP1

SWITCHING CHARACTERISTICS (T

A = -10 to 70° C; VA = 1.7 V - 3.3 V; Inputs: Logic 0 = GND,

Logic 1 = VL, CL = 20 pF)

16.

There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.

Parameters

Symbol

Min

Typ

Max

Units

Input Sample Rate

Single Speed Mode

Double Speed Mode

100

kHz

MCLK Pulse Width High

MCLK/LRCK = 1024

MCLK Pulse Width Low

MCLK/LRCK = 1024

MCLK Pulse Width High

MCLK/LRCK = 768

MCLK Pulse Width Low

MCLK/LRCK = 768

MCLK Pulse Width High

MCLK/LRCK = 512

MCLK Pulse Width Low

MCLK/LRCK = 512

MCLK Pulse Width High MCLK / LRCK = 384 or 192

MCLK Pulse Width Low

MCLK / LRCK = 384 or 192

MCLK Pulse Width High MCLK / LRCK = 256 or 128

MCLK Pulse Width Low

MCLK / LRCK = 256 or 128

Master Mode

SCLK Falling to LRCK Edge

tslrd

-20

SCLK Falling to SDOUT Valid

tsdo

SCLK Duty Cycle

Slave Mode

LRCK Duty Cycle

Rise Time of Both LRCK and SCLK

Fall Time of Both LRCK and SCLK

SCLK Period (Note 16)

Single Speed Mode

Double Speed Mode

tsclkw

SCLK Falling to LRCK Edge

tslrd

-20

SCLK Falling to SDOUT Valid

Single Speed Mode

Double Speed Mode

tdss

128

()Fs

----------------------

()Fs

------------------

(512)Fs

(256)Fs

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