CS22220 Wireless PCMCIA Controller

26 of 34

DS557PP2

Rev. 3.0

www.cirrus.com

Table 8. ROM/Flash Memory ‘Read’ Timing

Item

Symbol

Min

Max

Clock Period

(1)

72 MHz

103 MHz

CE to SMD Latched Data

(2)

221 ns

OE de-asserted to OE asserted

(3)

ROM address to output delay

(4)

220 ns

SMCLK to SMA output delay

4.0 ns

SMCLK to BRCE output delay (CE)

4.5 ns

SMCLK to SMRAS output delay (OE)

5.0 ns

SMD setup to SMCLK

1.0 ns

SMD hold from SMCLK

2.4 ns

1. The memclock timing is derived by bootstrap PLL settings. Synchronous modes at 77 MHz & 72

MHz are currently supported.

SMCLK = 221ns).

The ROM device must release the bus within this time frame (77MHz ~ 78 ns).

4. Based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register

settings for more information)

SMCLK

SMD[7:0]

SMA[11:0], SMD[13:8]

SMNWE

BRCE (CE)

SMRAS (OE)

DATA

ADDRESS

SMCLK

SMRAS

SMD

BRCE

SMRAS

BRCE

SMA

SMD

SMD

SMRAS

Figure 7. ROM Memory Interface 'Read' Timing Diagram