CS22210 PCI/USB Wireless Controller

29 of 31

D556PP2

Rev. 3.0

www.cirrus.com

Table 11. Radio MAC AC Timings – Intersil Modes

Parameter

Parameter Description

Min

Max

Units

BBAS output delay from falling BBSCLK

8.2

ns

BBRNW output delay from falling BBSCLK

8.0

ns

nBBCS output delay from falling BBSCLK

59.0

ns

BBSDX output delay from falling BBSCLK

7.0

ns

BBSDX setup to rising edge of BBSCLK

14.8

ns

BBSDX hold from rising edge of BBSCLK

0.0

ns

TXD output delay from rising TXCLK (SMAC

Mode)

33.5

ns

TXD output delay from rising TXCLK (RMAC

Mode)

15.4

ns

RXD setuptorising edgeofRXCLK

1.0

ns

RXD hold from rising edge of RXCLK

1.8

ns

MDRDY setup to falling edge of RXCLK

2

ns

MDRDY hold from falling edge of RXCLK

1

ns

TXPEBB output delay from rising TXCLK

15.0

ns

RXPEBB output delay from rising RXCLK

16.0

ns

TXRDY setup to falling edge of TXCLK

6.5

ns

TXRDY hold from falling edge of TXCLK

0

ns

2

RXCLK period

See Note

ns

2

TXCLK period

See Note

ns

Notes:

1.

CCA signal is double synchronized to ARMCLKIN.

2.

ARMCLK must be at least 4 times the TXCLK and RXCLK frequency.

3.

Harris baseband (3824/3824A) generates RXCLK and TXCLK of 4 Mhz. the duty cycle varies between 33-40%

with a high time of 90.9ns and low time that alternates between 136 and 182ns. The clock period varies between

227 and 272 ns, giving an effective period of 250ns.

4.

TXD delay in 802.11b mode is the result of sampling the TXCLK with the ctlclk, therefore the maximum delay

is equal to two ctlclk periods plus the flop-to-output delay. In this table, ctlclk is assumed to have a 13 ns period.

5.

BBNCS output delay = [(1/ARMCLK freq)*ceiling(SER_CLK_DIV/2)] + 7ns, the specified value is based on

ARMCLK of 77 Mhz and SER_CLK_DIV=8.