Figure 10. Bode plot of error amplifier (OTA) gain and modulator gain

added to the feedback resistor divider attenuation.

A pole at point C:

(8g)

offsets the zero set by the ESR of the output capacitors.

An alternative scheme uses a single capacitor as shown in

Figure 11, to roll the gain off at a relatively low frequency.

Figure 11. A typical application diagram with external components con-

figured in a boost topology.

Step 9

Finally the watchdog timer period and Power on Reset

time is determined by:

(9)

NC

NC

Gnd

Gnd

Gnd

Gnd

SELECT

COMP

Gnd

Gnd

Gnd

Gnd

WDI

100µF

ESR<8Ω

0.1µF

0.33µF

L=33µH

88µF

(2)

100kΩ

946Ω

7.5kΩ

390pF

RESET

ENABLE

(1)

MICROPROCESSOR

5V

Pole due to error amplifier

G

0

+G

B

A

C

error amplifier gain

-20dB/dec

-G

modulator gain + feedback resistor divider attenuation

9

Application Notes: continued

25

0

05

50

75

100

10

20

25

15

30

Max Total Power = 1.86W

25

0

05

50

75

100

10

20

25

15

30

Max Total Power = 1.18W

Worst Case Switcher

Worst Case Switcher

Linear Power

Power Available

Power Available

Dissipation

(V)

(V)

(mA)

(W)

(W)

(W)

20

14

25

0.44

0.74

1.42

20

14

50

0.83

0.35

1.03

20

14

75

1.22

*

0.64

20

14

100

1.60

*

0.26

25

14

25

0.60

0.58

1.26

25

14

50

1.11

0.07

0.75

25

14

75

1.62

*

0.24

25

14

100

2.14

*

*

Linear Regulator Output Current vs. Input Voltage

loads and voltages.

* Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit.