ML9271 datasheet(4/16 Pages) ETC2

4 / 16 page

FEDL9271-01

LAPIS Semiconductor

ML9271

4/16

PIN DESCRIPTION

Symbol

Type

Function

Description

1 to 17,

32 to 48,

50 to 63

HVO1

HVO48

Driver

Outputs

Driver output pins, which correspond to individual bits of the

shift register.

19,30

VDISP

—

Driver Power

Supply

Power supply pins for driver circuit. Both pin 19 and pin 30

should be connected externally.

VDD

—

Logic Power

Supply

Power supply pin for logic.

20,29

D-GND

—

Driver GND

GND pins for the driver circuits. Both pin 20 and pin 29 should

be connected externally.

L-GND

—

Logic GND

GND pin for the logic circuit.

DIN

Data Input

Input pin without pull-up or pull-down resistor. The input pin

to the shift register. Inputs to display data are synchronized

with the clock signal. (positive logic)

CLK

Clock Input

Input pin without pull-up or pull-down resistor. Data of the

shift register is shifted from one stage to the next on each

rising edge of the clock pulses.

Latch Strobe

Input

Input pin without pull-up or pull-down resistor. When LS is

high, the latch is shunted and the shift register outputs

become latched. The latch holds the outputs from the shift

Clear Input

Clear input pin with a pull-up resistor. This pin is normally

low. On this condition, driver output changes to high or low

according to the latch output level. When CL is high, all driver

output pins are fixed to low.

CHG

Test Input

Test input pin with a pull-down resistor. This pin is normally

low. When CL is high, all driver output pins are fixed to low

irrespective of CHG. When CL is low and CHG is low, the

driver outputs change to high or low according to the latch

output level. When CHG is high and CL is low, all driver

outputs are high for testing.

DOUT

Data Output

Serial output pin from the shift register.

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