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TNRLA024AE bảng dữ liệu(PDF) 17 Page - Renesas Technology Corp |
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TNRLA024AE bảng dữ liệu(HTML) 17 Page - Renesas Technology Corp |
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17 / 37 page ![]() RENESAS TECHNICAL UPDATE TN-RL*-A024A/E Date: Apr. 9, 2014 Page 17 of 37 5. Figure 14-1. Block Diagram of Comparator Incorrect names of the noise filter and the edge detection circuit in the block diagram are revised, and Note is added. Incorrect: CMPCOM/(CMP3P)Note/ ANI18/P147 CmVRS4 CmVRS5 CmVRS6 CmVRS3 CmVRS0 CmVRS2 CmVRS1 Comparator internal reference voltage select register m (CmRVM) CMPSEL0 Comparator input switch control register (CMPSEL) WCSEL0 WCSEL1 WCSEL2 Window comparator function setting register (CMPWDC) CVRE2 CVRVS0 CVRVS1 CVRE1 CVRE0 Comparator internal reference voltage control register (CVRCTL) + _ + _ INTCMP0 Edge detector Edge detector Edge detector Edge detector Edge detector Edge detector CMP0P/ANI2/P22 INTP20/P10 INTP21/P11 0 1 Noise filter Noise filter C0OE C0INV C0MOD SEL0 CMP0EN C0DFS1 C0DFS0 C0MOD SEL1 Comparator 0 control register (C0CTL) Comparator 0 DA0 DA1 DA2 CEGP0 CEGN0 Comparator rising edge enable register (CMPEGP0) Comparator falling edge enable register (CMPEGN0) CMP0 output Timer output forced stop request signal (timers KB0 to KB2) INTCMP1, Timer restart request signal (timer KB0) Timer restart request signal (timers KB0 to KB2) CMP1P/ANI4/P24 Comparator 1 Timer output forced stop request signal (timer KB0) CMPMON0 Comparator output monitor register (CMPMON) Edge detector 0 1 1 0 1 0 0 1 1 0 External interrupt INTP20, INTP21 control block CEGP6 CEGN6 CEGP7 CEGN7 Comparator rising edge enable register (CMPEGP0) Comparator falling edge enable register (CMPEGN1) Timer output forced stop request signal (timers KB0 to KB2) Timer restart request signal (timers KB0 to KB2) INTP20 INTP21 Edge detector 0 1 Timer output forced stop request signal (timers KB0 to KB2) INTPINV1INTPINV0 External interrupt control register (INTPCTL) External interrupt edge enable register (EGP2, EGN2) TMR STEN0 TMR STEN1 PNFEN Peripheral function switch register 0 (PFSEL0) Timer restart request signal (timer KB1) CMP2P/ANI5/P25 Comparator 2 Timer output forced stop request signal (timers KB0, KB1) INTCMP3, Timer restart request signal (timer KB2) CMP3P/ANI6/P26 Comparator 3 Timer output forced stop request signal (timer KB1) INTCMP4 CMP4P/ANI7/P27 Comparator 4 Timer output forced stop request signal (timer KB2) INTCMP5 CMP5P/ANI16/RxD1/P03 Comparator 5 Timer output forced stop request signal (timer KB2) VDD AVREFP/ANI0/P20 CVREm bit AVREFM/ANI1/P21 VSS WCSEL0 bit WCSEL2 bit WCSEL1 bit DA0 DA1 DA2 + _ + _ + _ + _ Note Noise filter CMP0 STEN CMP2 STEN CMP0STEN CMP2STEN Peripheral function switch register 0 (PFSEL0) INTCMP2 0 1 Edge detector Note 20-pin products only. ANI16/CMP3P/P26 is selected by default for 30- and 38-pin products. Remark m = 0 to 2 |
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