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TNA086AE bảng dữ liệu(PDF) 13 Page - Renesas Technology Corp

tên linh kiện TNA086AE
Giải thích chi tiết về linh kiện  MPU/MCU
PDF  16 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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TNA086AE bảng dữ liệu(HTML) 13 Page - Renesas Technology Corp

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RENESAS TECHNICAL UPDATE TN-RX*-A086A/E
Date: Jan. 30, 2014
Page 13 of 16
Add a chapter in ‘29.12 Usage Notes’.
35.12.14 Note in Relation to Transmit Enable Bit (TE)
When the SCR.TE bit is set to 0 (serial transmission disabled) with a pin functions as TXDn (n = 0 to 3, 12), the pin output
goes high impedance.
To avoid the TXDn line going high impedance, take any of the following methods.
(1) Connect pull-up resistor to the TXDn line.
(2) Before setting the SCR.TE bit to 0, modify the pin function to "general I/O port, output", or, after setting the
SCR.TE bit to 1, modify the pin function to TXDn.
Page 1364
Correct a description in ‘Table 31.8 Operation in CAN Reset Mode and CAN Halt Mode’.
Mode
Receiver
Transmitter
Transmitter
CAN reset mode
(forcible transition)
CANM[1:0] = 11b
CAN module enters CAN reset
mode without waiting for the end of
message reception.
CAN module enters CAN reset
mode without waiting for the end of
message transmission.
CAN module enters CAN reset
mode without waiting for the end of
bus-off recovery.
CAN reset mode
CANM[1:0] = 01b
CAN module enters CAN reset
mode without waiting for the end of
message reception.
CAN module enters CAN reset
mode after waiting for the end of
message transmission.*1,*4
CAN module enters CAN reset
mode without waiting for the end of
bus-off recovery.
CAN halt mode
CAN module enters CAN halt mode
after waiting for the end of message
reception.*2,*3
CAN module enters CAN halt mode
after waiting for the end of message
transmission.*1,*2,*4
[When the BOM[1:0] bits are 00b]
A halt request from a program will be
accepted only after bus-off recovery.
[When the BOM[1:0] bits are 01b]
CAN module automatically enters
CAN halt mode without waiting for
the end of bus-off recovery
(regardless of a halt request from a
program).
[When the BOM[1:0] bits are 10b]
CAN module automatically enters
CAN halt mode after waiting for the
end of bus-off recovery (regardless
of a halt request from a program).
[When the BOM[1:0] bits are 11b]
CAN module enters CAN halt mode
(without waiting for the end of busoff
recovery) if a halt is requested by
a program during bus-off.
CANM[1:0], BOM[1:0]: Bits in CTLR
Note 1. If several messages are requested to be transmitted, mode transition occurs after the completion of the first message
transmission. In a case that the CAN reset mode is being requested during suspend transmission, mode transition occurs when
the bus is idle, the next transmission ends, or the CAN module becomes a receiver.
Note 2. If the CAN bus is locked in dominant state, the program can detect this state by monitoring the EIFR.BLIF flag. The CAN module
does not enter CAN halt mode while the CAN bus is locked in dominant state. Enter CAN reset mode instead.
Note 3. If a CAN bus error occurs during reception after CAN halt mode is requested, the CAN module enters CAN halt mode. However,
the CAN module does not enter CAN Halt mode when the CAN bus is locked in dominant state.
Note 4. If a CAN bus error or arbitration-lost occurs during transmission after CAN reset mode or CAN halt mode is requested, the CAN
module enters the requested operating mode. However, the CAN module does not enter CAN Halt mode when the CAN bus is
locked in dominant state.
Page 1251



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