RX62N Group and RX621 Group

16-Bit SDRAM Connection and Access Examples

R01AN0585EJ0202 Rev.2.02

Page 13 of 22

Feb 14, 2014

5.4

Registers Used

The tables below lists the registers used by this application note. Note that the setting values shown are the ones used in

this application note and differ from the initial values.

(1)

Clock generation circuit

System clock control register (SCKCR)

Bits: 32, Address: 0008 0020h

Bit

Symbol

Setting

Name

Function

R/W

b11-b8

PCK[3:0]

0001

Peripheral module clock

selection bits

0001:

× 4

PCLK = 48 MHz

(When the EXTAL clock is 12 MHz)

R/W

b19-b16

BCK[3:0]

0001

External bus clock and

SDRAM selection bits

0001:

× 4

BCLK, SDCLK = 48 MHz

(When the EXTAL clock is 12 MHz)

R/W

b22

PSTOP0

0

SDCLK pin output control bit

0: SDCLK output pin operates

R/W

b27-b24

ICK[3:0]

0000

System clock selection bits

0000:

× 8

ICLK = 96 MHz

(When the EXTAL clock is 12 MHz)

R/W

(2)

Operating mode

System control register 0 (SYSCR0)

Bits: 8, Address: 0008 0006h

Bit

Symbol

Setting

Name

Function

R/W

b0

ROME

1

Internal ROM enable bit

1: Internal ROM enabled

R/W

b1

EXBE

1

External bus enable bit

1: External bus enabled

R/W

b15-b8

KEY[7:0]

5Ah

SYSCR0 key code

5Ah: SYSCR0 register write enabled

R/W