5CSXFC6D datasheet(35/35 Pages) ALTERA

35 / 35 page

Changes

Version

Date

• Restructured the document.

• Added the “Embedded Memory Capacity” and “Embedded Memory

Configurations” sections.

• Added Table 1, Table 3, Table 16, Table 19, and Table 20.

• Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9,

Table 10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table

18.

• Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, and

Figure 10.

• Updated the “FPGA Configuration and Processor Booting” and

“Hardware and Software Development” sections.

• Text edits throughout the document.

2.0

June 2012

• Updated Table 1–2, Table 1–3, and Table 1–6.

• Updated “Cyclone V Family Plan” on page 1–4 and “Clock Networks

and PLL Clock Sources” on page 1–15.

• Updated Figure 1–1 and Figure 1–6.

1.2

February 2012

• Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, Table 1–5, and

Table 1–6.

• Updated Figure 1–4, Figure 1–5, Figure 1–6, Figure 1–7, and Figure

1–8.

• Updated “System Peripherals” on page 1–18, “HPS–FPGA AXI Bridges”

on page 1–19, “HPS SDRAM Controller Subsystem” on page 1–19,

“FPGA Configuration and Processor Booting” on page 1–19, and

“Hardware and Software Development” on page 1–20.

• Minor text edits.

1.1

November 2011

Initial release.

1.0

October 2011

Altera Corporation

Cyclone V Device Overview

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Document Revision History

CV-51001

2013.12.26

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