FEDL9489-02

ML9489

15/32

List of Commands

Command

name

C7

C6

C5

C4

C3

C2

C1

C0

Operation

F0

0

0

0

0

x

x

x

x

Disabled

F1

0

1

F1

(*2)

F0

(*2)

x

x

x

x

Frame frequency setting

(F1,F0)=(0, 0): 130Hz

(F1,F0)=(0, 1): 150Hz

(F1,F0)=(1, 0): 170Hz

(F1,F0)=(1, 1): 190Hz

(valid for Internal CR oscillation)

F2

1

0

1

D

(*2)

x

x

x

x

Display on/off

"0" : Off （COM=SEG=GND）

"1" : On

F3(*1)

1

1

SA1

SA0

A1

A0

Co1

Co0

Data write address setting

(Co1,Co0)=(0, 0): Corresponding to

common 1

(Co1,Co0)=(0, 1): Corresponding to

common 2

(Co1,Co0)=(1, 0): Corresponding to

common 3

(Co1,Co0)=(1, 1): Corresponding to

common 4

SA1, SA0, A1, A0: Chip address

x: Don't care

These bits become "Don't care".

In the ML9489, set the SA1 address to "1".

(*2): The register is set to the following value by the RESETB = "L" input or by the power-on POC.

F1="0", F0="0", D="0"

Data configuration

• Data configuration (Serial interface)

D160 D159

D158

D3

D2

D1

C0

C1

C2

C3

C4

C5

Command

LCD display data

Corresponding to SEG1

Corresponding to SEG160

First bit

C6

C7

Note 1 : The commands F1 and F2 settings become valid when the least four bits of C4 to C7 are input.

(The bits from D1 to D160 and from C0 to C3 are not necessary.)

Note 2 : If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side.

Note 3 : The command execution follows the contents of the C7 to C0 registers immediately before the LOAD

becomes "H".