5-551

FAST AND LS TTL DATA

4-BIT SHIFT REGISTER

WITH 3-STATE OUTPUTS

The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate

in either a synchronous parallel load or a serial shift-right mode, as

determined by the Select input. An asynchronous active LOW Master Reset

(MR) input overrides the synchronous operations and clears the register. An

active HIGH Output Enable (OE) input controls the 3-state output buffers, but

does not interfere with the other operations. The fourth stage also has a

conventional output for linking purposes in multi-stage serial operations.

CONNECTION DIAGRAM DIP (TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

MR

O0 O1

O2

O3

CP

Q3

OE

DS

P0

P1

P2

P3

S

GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

P0 – P3

DS

S

CP

MR

OE

O0 – O3

Q3

Parallel Inputs

Serial Data Input

Mode Select Input

Clock (Active LOW) Input

Master Reset (Active LOW) Input

Output Enable (Active HIGH) Input

3-State Register Outputs

Register Output

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

65 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

15 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

SN74LS395

4-BIT SHIFT REGISTER

WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN74LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

1

2

3 4 5 6

10

9

15 14 13 12

11

7

S P0 P1 P2 P3

DS

CP

OE

MR O0 O1 O2 O3

Q3