80L188EC datasheet(11/57 Pages) INTEL

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80C186EC188EC 80L186EC188EC

Table 2 Pin Descriptions

(Continued)

Pin Name

Input

Output

Pin Description

Type

States

A18S5

A(L)

H(Z)

These pins drive address information during the address

phase of the bus cycle During T2 and T3 these pins drive

A17S4

R(WH)

status information (which is always 0 on the 80C186EC)

A16S3

I(0)

These pins are used as inputs during factory test driving

(A158)

P(0)

these pins low during reset will cause unspecified operation

On the 80C188EC A158 provide valid address information

for the entire bus cycle

AD15CAS2

S(L)

H(Z)

These pins are part of the multiplexed ADDRESS and DATA

bus During the address phase of the bus cycle address bits

AD14CAS1

R(Z)

15 through 13 are presented on these pins and can be

AD13CAS0

I(0)

latched using ALE Data information is transferred during the

P(0)

data phase of the bus cycle Pins AD1513CAS20 drive the

82C59 slave address information during interrupt

acknowledge cycles

AD120

S(L)

H(Z)

These pins provide a multiplexed ADDRESS and DATA bus

During the address phase of the bus cycle address bits 0

(AD70)

R(Z)

through 12 (0 through 7 on the 80C188EC) are presented on

I(0)

the bus and can be latched using ALE Data information is

P(0)

transferred during the data phase of the bus cycle

S20

H(Z)

Bus cycle Status are encoded on these pins to provide bus

transaction information S20 are encoded as follows

R(1)

I(1)

P(1)

Bus Cycle Initiated

Interrupt Acknowledge

Read IO

Write IO

Processor HALT

Instruction Queue Fetch

Read Memory

Write Memory

Passive (No bus activity)

ALE

H(0)

Address Latch Enable

output is used to strobe address

information into a transparent type latch during the address

R(0)

phase of the bus cycle

I(0)

P(0)

BHE

H(Z)

Byte High Enable

output to indicate that the bus cycle in

progress is transferring data over the upper half of the data

(RFSH)

R(Z)

bus BHE and A0 have the following logical encoding

I(1)

P(1)

BHE

Encoding

(for 80C186EC

80L186EC only)

Word transfer

Even Byte transfer

Odd Byte transfer

Refresh operation

On the 80C188EC80L188EC RFSH is asserted low to

indicate a refresh bus cycle

NOTE

Pin names in parentheses apply to the 80C188EC80L188EC

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