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54LS196 bảng dữ liệu(PDF) 5 Page - Motorola, Inc

tên linh kiện 54LS196
Giải thích chi tiết về linh kiện  4-STAGE PRESETTABLE RIPPLE COUNTERS
PDF  6 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

54LS196 bảng dữ liệu(HTML) 5 Page - Motorola, Inc

  54LS196 Datasheet HTML 1Page - Motorola, Inc 54LS196 Datasheet HTML 2Page - Motorola, Inc 54LS196 Datasheet HTML 3Page - Motorola, Inc 54LS196 Datasheet HTML 4Page - Motorola, Inc 54LS196 Datasheet HTML 5Page - Motorola, Inc 54LS196 Datasheet HTML 6Page - Motorola, Inc  
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FAST AND LS TTL DATA
SN54/74LS196
• SN54/74LS197
AC CHARACTERISTICS (TA = 25°C)
Sb l
P
Limits
Ui
T
C
di i
Sb l
P
LS196
LS197
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
30
40
30
40
MHz
V5 0 V
tPLH
tPHL
CP0 Input to
Q0 Output
8.0
13
15
20
8.0
14
15
21
ns
V5 0 V
tPLH
tPHL
CP1 Input to
Q1 Output
16
22
24
33
12
23
19
35
ns
V5 0 V
tPLH
tPHL
CP1 Input to
Q2 Output
38
41
57
62
34
42
51
63
ns
VCC = 5.0 V
tPLH
tPHL
CP1 Input to
Q3 Output
12
30
18
45
55
63
78
95
ns
CC
CL = 15 pF
tPLH
tPHL
Data to Output
20
29
30
44
18
29
27
44
ns
tPLH
tPHL
PL Input to
Any Output
27
30
41
45
26
30
39
45
ns
tPHL
MR Input to Any Output
34
51
34
51
ns
AC SETUP REQUIREMENTS (TA = 25°C)
Sb l
P
Limits
Ui
T
C
di i
Sb l
P
LS196
LS197
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Test Conditions
tW
CP0 Pulse Width
20
20
ns
V5 0 V
tW
CP1 Pulse Width
30
30
ns
V5 0 V
tW
PL Pulse Width
20
20
ns
V5 0 V
tW
MR Pulse Width
15
15
ns
V5 0 V
ts
Data Input Setup Time — HIGH
10
10
ns
VCC = 5.0 V
ts
Data Input Setup Time — LOW
15
15
ns
th
Data Hold Time — HIGH
10
10
ns
th
Data Hold Time — LOW
10
10
ns
trec
Recovery Time
30
30
ns
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.



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