5-366

FAST AND LS TTL DATA

UNIVERSAL 4-BIT

SHIFT REGISTER

The SN54 / 74LS195A is a high speed 4-Bit Shift Register offering typical

shift frequencies of 39 MHz. It is useful for a wide variety of register and

counting applications. It utilizes the Schottky diode clamped process to

achieve high speeds and is fully compatible with all Motorola TTL products.

CONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

MR

Q0

Q1

Q2

Q3

CP

Q3

PE

J

K

P0

P1

P2

P3 GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

PE

Parallel Enable (Active LOW) Input

0.5 U.L.

0.25 U.L.

P0 – P3

Parallel Data Inputs

0.5 U.L.

0.25 U.L.

J

First Stage J (Active HIGH) Input

0.5 U.L.

0.25 U.L.

K

First Stage K (Active LOW) Input

0.5 U.L.

0.25 U.L.

CP

Clock (Active HIGH Going Edge) Input

0.5 U.L.

0.25 U.L.

MR

Master Reset (Active LOW) Input

0.5 U.L.

0.25 U.L.

Q0 – Q3

Parallel Outputs (Note b)

10 U.L.

5 (2.5) U.L.

Q3

Complementary Last Stage Output (Note b)

10 U.L.

5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

SN54/74LS195A

UNIVERSAL 4-BIT

SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

2

10

3

4 5 6 7

11

12

13

14

15

1

9

J

PE

CP

K MR

P0 P1 P2 P3

Q0 Q1 Q2 Q3

Q3

VCC = PIN 16

GND = PIN 8