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SN74LS156D bảng dữ liệu(PDF) 2 Page - Motorola, Inc

tên linh kiện SN74LS156D
Giải thích chi tiết về linh kiện  DUAL 1-OF-4 DECODER/ DEMULTIPLEXER
PDF  6 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

SN74LS156D bảng dữ liệu(HTML) 2 Page - Motorola, Inc

  SN74LS156D Datasheet HTML 1Page - Motorola, Inc SN74LS156D Datasheet HTML 2Page - Motorola, Inc SN74LS156D Datasheet HTML 3Page - Motorola, Inc SN74LS156D Datasheet HTML 4Page - Motorola, Inc SN74LS156D Datasheet HTML 5Page - Motorola, Inc SN74LS156D Datasheet HTML 6Page - Motorola, Inc  
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FAST AND LS TTL DATA
SN54/74LS155
• SN54/74LS156
LOGIC DIAGRAM
Ea Ea
A0 A1
EbEb
O0a
O1a
O2a
O3a
O0b
O1b
O2b
O3b
14
1
2
6
7
3
4
5
9
11
12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti-
plexers with common Address inputs and separate gated
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four
mutually exclusive active LOW outputs (O0–O3). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (Ea•Ea). In demultiplexing applica-
tions, Decoder “a” can accept either true or complemented
data by using the Ea or Ea inputs respectively. The enable gate
for Decoder “b” requires two active LOW inputs (Eb•Eb). The
LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti-
plexer by tying Ea to Eb and relabeling the common connection
as (A2). The other Eb and Ea are connected together to form
the common enable.
The LS155 and LS156 can be used to generate all four
minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
Figure a
E
A0
A1
E
A0
A1
E
A0
A1
E
A0
A1
O0
O1
O2
O3
E
A0
A1
E
A0
A1
E
A0
A1
E
A0
A1
O0
O1
O2
O3
TRUTH TABLE
ADDRESS
ENABLE “a”
OUTPUT “a”
ENABLE “b”
OUTPUT “b”
A0
A1
Ea
Ea
O0
O1
O2
O3
Eb
Eb
O0
O1
O2
O3
X
X
L
X
H
H
H
H
H
X
H
H
H
H
X
X
X
H
H
H
H
H
X
H
H
H
H
H
L
L
H
L
L
H
H
H
L
L
L
H
H
H
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
L
L
H
H
L
H
H
H
H
L
H
H
H
L
L
L
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care



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