LTC1289BCSW datasheet(14/28 Pages) LINER

14 / 28 page

LTC1289

1289fb

APPLICATI

I FOR ATIO

Deglitcher

A deglitching circuit has been added to the Chip Select

input of the LTC1289 to minimize the effects of errors

caused by noise on that input. This circuit ignores changes

in state on the CS input that are shorter in duration than

one ACLK cycle. After a change of state on the CS input, the

LTC1289 waits for two falling edge of the ACLK before

recognizing a valid chip select. One indication of CS

recognition is the DOUT line becoming active (leaving the

Hi-Z state). Note that the deglitching applies to both the

rising and falling CS edges.

CS Low During Conversion

In the normal mode of operation, CS is brought high

during the conversion time. The serial port ignores any

SCLK activity while CS is high. The LTC1289 will also

operate with CS low during the conversion. In this mode,

SCLK must remain low during the conversion as shown in

the following figure. After the conversion is complete, the

DOUT line will become active with the first output bit. Then

the data transfer can begin as normal.

Figure 4. CS Low During Conversion

Figure 3. CS High During Conversion

Low CS Recognized Internally

High CS Recognized Internally

ACLK

DOUT

Hi-Z

VALID OUTPUT

LTC1289 AI08

ACLK

DOUT

Hi-Z

VALID OUTPUT

LTC1289 AI08a

DON'T CARE

B11 B10 B9

SHIFT RESULT OUT

AND NEW ADDRESS IN

SCLK

DOUT

DIN

tSMPL

SAMPLE ANALOG

INPUT

SHIFT

MUX ADDRESS

LTC1289 AIF03

48 TO 52

ACLK CYC

DON'T CARE

B11 B10 B9

B8B7

B3B2

B1B0

SHIFT RESULT OUT

AND NEW ADDRESS IN

SCLK

DOUT

DIN

tSMPL

SAMPLE ANALOG

INPUT

SHIFT

MUX ADDRESS

LTC1289 AIF04

48 TO 52

ACLK CYC

SCLK MUST

REMAIN LOW

LTC1289BCSW bảng dữ liệu(PDF) 14 Page - Linear Technology

LTC1289BCSW bảng dữ liệu(HTML) 14 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

bảng dữ liệu tải về

Link URL