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IS15ABFP4RGB bảng dữ liệu(PDF) 2 Page - List of Unclassifed Manufacturers |
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IS15ABFP4RGB bảng dữ liệu(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 4 page  SMARTSWITCHTM NKK Switches • email: smartswitch@nkkswitches.com • Phone (480) 991-0942 • Fax (480) 998-1435 • www.nkksmartswitch.com 2 LCD SPECIFICATIONS Characteristics of Display Display Operation Mode FSTN positive Display Condition Transflective with built-in LED backlight Viewing Angle Adjustable Driving Method 1/24 duty. 1/5 bias (built-in driving circuit) Viewing Area 15.0mm x 10.8mm (horizontal x vertical) Pixel Format 36 x 24 dots (horizonal x vertical) Pixel Size 0.36mm x 0.36mm (horizontal x vertical) Backlight LED Red/Green/Blue RGB LED with Black & White LCD Mode Absolute Maximum Ratings (Temperature at 25°C) Items Symbols Ratings Supply Voltage for Logics VDD – 0.3V to +7.0V Supply Voltage for LCD VLC – 0.3V to +12.0V Input Voltage VI – 0.3V to VDD +0.3V Output Voltage VO – 0.3V to VDD +0.3V Recommended Operating Conditions (Temperature at 25°C) Items Symbols Minimum Typical Maximum Supply Voltage for Logics VDD 4.5V 5.0V 5.5V Supply Voltage Black/White VLC –– 7.3V –– Input Voltage VI 0V –– VDD Driving Frequency fFLM –– 150Hz –– DC Characteristics of LCD Drive IC (Temperature at 0°C to 40°C and V DD = 5.0V ±10%) Items Symbols Test Conditions Minimum Typical Maximum Unit High Level Input Voltage VIH 0.7 VDD VDD V Low Level Input Voltage VIL 0 0.3 VDD V High Level Input Leakage Current ILIH VI = VDD 10 μA Low Level Input Leakage Current ILIL VI = 0V –10 μA High Level Output Voltage VOH IOH = –500μA VDD – 0.5 V Low Level Output Voltage VOL IOL = 500μA 0.5 V High Level Output Leakage Current ILOH VO = VDD 10 μA Low Level Output Leakage Current ILOL VO = 0V –10 μA Supply Current IDD fSCP = 1.0MHz 500 μA LCD Drive Current ILC fLP = 2.4kHz VLC = 7.3V ~ 7.5V 500 2,000 μA Timing Characteristics of LCD Drive IC (Temperature at 0°C to 40°C and VDD = 5.0V ±10%) Items Symbols Minimum Maximum Clock Operation Frequency fSCP 6.0MHz Latch Pulse Frequency f LP 50kHz Clock High Level Pulse Width tCWH 70ns Clock Low Level Pulse Width tCWL 70ns Data Setup Time tDSD 45ns Data Hold Time tDHD 50ns Data Output Delay Time tPDO 25ns Latch Setup Time tDSL 50ns Latch Hold Time tDHL 50ns Latch High Level Width tLWH 200ns FLM Setup Time tDSF 50ns FLM Hold Time tDHF 50ns SCP, LP Rise/Fall Time tr/tf 15ns Timing Diagram *1 Last data on first line *2 Beginning data on second line *3 Location of LP signal on first line tLWH tCWL tDSF tDHF tr tf *3 tDSL tDHL *2 *1 tPDO tDHD tDSD tCWH tr tf SCP Din Dout LP FLM |
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