ATMEGA161-4AI datasheet(33/134 Pages) ATMEL

33 / 134 page

ATmega161(L)

Note:

When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Other-

wise an interrupt can occur when the bits are changed.

• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set.

The level and edges on the external INT0 pin that activate the interrupt are defined in Table 8. The value on the INT0 pin is

sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low

level must be held until the completion of the currently executing instruction to generate an interrupt.

Note:

When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Other-

wise an interrupt can occur when the bits are changed.

Extended MCU Control Register – EMCUCR

The Extended MCU Control Register contains control bits for external interrupt 2, sleep mode bit and control bits for the

external memory interface.

• Bit 7 - SM0: Sleep mode bit 0

When this bit is set (one) and sleep mode bit 1 (SM1) in MCUCR is set, Power Save Mode is selected as sleep mode.

Refer to page 34 for a detailed description of the sleep modes.

• Bit 6..4 - SRL2, SRL1, SRL0: External SRAM limit

It is possible to configure different wait-states for different external memory addresses in ATmega161. The SRL2 – SRL0

bits are used to define at which address the different wait-states will be configured. See “Interface to external memory” on

page 72 for a detailed description.

• Bit 3..1 - SRW01, SRW00, SRW11: External SRAM wait-state select bits.

The SRW01, SRW00 and SRW11 bits are used to set up extra wait states in the external memory interface. See “Interface

to external memory” on page 72 for a detailed description.

• Bit 0 - ISC2: Interrupt Sense Control 2

The external interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding interrupt mask in the

GIMSK are set. If ISC2 is cleared (zero) a falling edge on INT2 activates the interrupt. If ISC2 is set (one) a rising edge on

INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than 50 ns will generate

an interrupt. Shorter pulses are not guaranteed to generate an interrupt.

Table 7. Interrupt 1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

Table 8. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Bit

543

210

$36 ($56)

SM0

SRL2

SRL1

SRL0

SRW01

SRW00

SRW11

ISC2

EMCUCR

Read/Write

R/W

Initial value

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