AT90LS2323 datasheet(16/64 Pages) ATMEL

16 / 64 page

AT90S/LS2323/2343

1004D–09/01

Memory Access and

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external

clock signal applied to the CLOCK pin. No internal clock division is used.

Figure 21. shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power unit.

Figure 21. The Parallel Instruction Fetches and Instruction Executions

Figure 22. shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed and the result is stored back

to the destination register.

Figure 22. Single Cycle ALU Operation

The internal data SRAM access is performed in two System Clock cycles as described

in Figure 23..

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

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