ATF1516AS/L

6

1. The V

2. After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and,

3. The clock must remain stable during T

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF1516AS fuse patterns. Once programmed, fuse

verify is inhibited. However, User Signature and device ID

remains accessible.

Programming

ATF1516AS devices are In-System Programmable (ISP)

devices utilizing the 4-pin JTAG protocol. This capability

eliminates package handling normally required for program

and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow pro-

gramming of the ATF1516AS via the PC. ISP is perfomed

by using either a download cable, or a comparable board

tester or a simple microprocessor interface.

To facilitate ISP programming by the Automated Test

Equipment (ATE) vendors. Serial Vector Format (SVF)

files can be created by Atmel provided Software utilities.

ATF1516AS devices can also be programmed using stan-

dard 3rd party programmers. With 3rd party programmer

the JTAG ISP port can be disabled thereby allowing 4 addi-

tional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD

applications for details.

ISP Programming Protection

The ATF1516AS has a special feature which locks the

device and prevents the inputs and I/O from driving if the

programming process is interrupted due to any reason. The

inputs and I/O default to high-Z state during such a condi-

tion. In addition the pin keeper option preserves the former

state during device programming.

All ATF1516AS devices are initially shipped in the erased

state thereby making them ready to use for ISP.

Note:

For more information refer to the “Desigining for In-Sys-

tem Programmability with Atmel CPLDs” application

note.

Timing Model

U