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LP38851 bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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LP38851 bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 29 page ![]() + R2 R1 1 x = V V ADJ OUT ¸ ¹ · ¨ © § ¸ © § ¨ ¨ ¹ · LP38851 www.ti.com SNVS492C – JUNE 2007 – REVISED APRIL 2013 Figure 30. FZERO and FPOLE vs Gain SETTING THE OUTPUT VOLTAGE (Refer to TYPICAL APPLICATION CIRCUIT) The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: (5) The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of VADJ is specified, the use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable. It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 k Ω. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZ pole set by R1 and CFF. ( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ (6) Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. Table 1. VOUT R1 R2 CFF FZ 0.8V 1.07 k Ω 1.78 k Ω 220 pF 676 kHz 0.9V 1.50 k Ω 1.87 k Ω 180 pF 589 kHz 1.00V 1.00 k Ω 1.00 k Ω 270 pF 589 kHz 1.1V 1.65 k Ω 1.37 k Ω 150 pF 643 kHz 1.2V 1.40 k Ω 1.00 k Ω 180 pF 631 kHz 1.3V 1.15 k Ω 715 Ω 220 pF 629 kHz 1.4V 1.07 k Ω 590 Ω 220 pF 676 kHz 1.5V 2.00 k Ω 1.00 k Ω 120pF 663 kHz 1.6V 1.65 k Ω 750 Ω 150 pF 643 kHz 1.7V 2.55 k Ω 1.07 k Ω 100 pF 624 kHz 1.8V 2.94 k Ω 1.13 k Ω 82 pF 660 kHz Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: LP38851 |
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