TSL3301CL

102 × 1 LINEAR OPTICAL SENSOR ARRAY

WITH ANALOG-TO-DIGITAL CONVERTER

TAOS141 − JULY 2011

10

r

r

Copyright

E 2011, TAOS Inc.

The LUMENOLOGY

r Company

www.taosinc.com

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

A-to-D converter resolution

8

Bits

Full scale reference

Gain register = 00000b

3.6

Full-scale reference

Gain register = 11111b

1.24

Full-scale reference temperature sensitivity

For converter only, does not include

photodiode characteristics

±150

ppm/

°C

Average dark level offset

Gain register = 00000b

Offset register

00000000b

0

7

30

LSB

Average dark-level offset

Gain register = 11111b

Offset register = 00000000b

20

LSB

Dark signal nonuniformity (DSNU)

Gain register = 00000b, see Note 1

5

10

LSB

Dark signal nonuniformity (DSNU)

Gain register = 11111b, see Note 1

14

LSB

Average white level output

Offset register =

Gain register = 00000b

Ee = 11.3

160

200

240

LSB

Average white level output

Offset register =

00000000b

Gain register = 11111b

Ee = 3.77

200

LSB

Pixel-response non-uniformity (PRNU)

Ee = 11.3

±8

±10

%

Programmable offset steps

±128

Programmable offset step size

Gain register = 00000b

0.5

LSB

Programmable offset step size

Gain register = 11111b

1.5

LSB

Dark-level change with temperature

0

2

LSB

Differential nonlinearity

±0.5

LSB

Integral nonlinearity

±1

LSB

Dark level noise

Gain register = 00000b

0.5

LSB

Dark level noise

Gain register = 11111b

1.5

LSB

NOTES: 1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not

illuminated.

2. PRNU does not include DSNU.

3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly

illuminated at nominal white level (typical average output level = 200).

Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)

MIN

NOM

MAX

UNIT

Maximum clock frequency

10

MHz

Clock high pulse duration

30

ns

Clock low pulse duration

30

ns

Input setup time

20

ns

Input hold time

20

ns

Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rise time, output

C

20 pF

10

ns

Fall time, output

10

ns

Delay from clock edge to data-out stable

20

ns

Input pin capacitance

10

pF