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V6212615-01XE-R bảng dữ liệu(PDF) 20 Page - Texas Instruments |
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V6212615-01XE-R bảng dữ liệu(HTML) 20 Page - Texas Instruments |
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20 / 92 page ![]() T2.2.4 T2.2.1 32 clocks T2.2.2 T2.2.3 Input Output V CC X1 clock Hardware RESET_N MDC Latch-in of hardware configuration pins Dual function pins become enabled as outputs DP83848-EP SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013 www.ti.com 3.5.2 Reset Timing Figure 3-3. Reset Timing xxx PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.2.1 Post RESET Stabilization time prior to MDIO is pulled high for 32-bit serial 3 µs MDC preamble for register accesses management initialization T2.2.2 Hardware Configuration Latchin Time Hardware Configuration Pins are described 3 µs from the Deassertion of RESET (either in the Pin Description section soft or hard) T2.2.3 Hardware Configuration pins transition 50 ns to output drivers T2.2.4 RESET pulse width X1 Clock must be stable for at min. of 1µs 1 µs during RESET pulse low time (1) It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver. 20 ELECTRICAL SPECIFICATIONS Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848-EP |
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