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AS8525

Datasheet - Detailed Descr i p ti on

7.8 VCC Under-Voltage Reset

When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is

shutdown and temporary shutdown only through VCC under-voltage.

VCC under-voltage reset thresholds (VUVR_ON and VUVR_OFF) can be chosen by OTP.

7.9 Window Watchdog (WWD)

The Window Watchdog ensures that the Microcontroller is properly functioning in the normal mode of the device. The Watchdog is started after a

reset and the Microcontroller needs to send a trigger in the window of WD_TSV (service time). If the trigger occurs early, in the period WD_TCL,

or after WD_TSV, a reset output is generated.

The Microcontroller can access the trigger bit for the watchdog through SPI. The WWD can be enabled and the window times can be

programmed through OTP bits.

Figure 7. Window Watchdog Functionality

7.10 Timeout Watchdog (TWD)

The Timeout Watchdog ensures that the Microcontroller is in proper functional state in the device standby mode. The Watchdog timer will be

started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout.

The Microcontroller can access the trigger bit for the watchdog through SPI. The TWD can be enabled by OTP and the timeout interval can be

programmed through SPI.

Period

Non-Service time (WD_TCL)

Service time (WD_TSV)

Trigger

restart

period

Trigger

via SPI

Last trigger

Earliest point for

correct trigger

(No RESET)

50 %

100 %

Wrong trigger

(RESET generation)

Correct trigger

(No RESET)

Latest point for

correct trigger

(No RESET)

Wrong trigger

(RESET generation)