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AS5134 bảng dữ liệu(PDF) 7 Page - ams AG

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AS5134 bảng dữ liệu(HTML) 7 Page - ams AG

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www.austriamicrosystems.com/AS5134
Revision 2.3
6 - 32
AS5134
Datasheet - Electrical Character i s t ics
6.1 Timing Characteristics
CMOS Outputs: DIO, PWM, DX
VOH
High level output voltage
Source current < 4mA
VDD-0.5
VDD
V
VOL
Low level output voltage
Sink current < 4mA
0
VSS+0.4
V
CL
Capacitive load
35
pF
CMOS Tristate Output: DIO
IOZ
Tristate leakage current
CS = low
1
µA
Table 4. Timing Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
2-/3-Wire Data Transmission
3-Wire Interface
fDCLK
Clock Frequency
Normal operation
5
6
MHz
fDCLK,P
Clock Frequency
During OTP programming
200
650
kHz
2-Wire Interface
fDCLK
Clock Frequency
Normal operation
0.1
5
6
MHz
fDCLK,P
Clock Frequency
During OTP programming
200
500
kHz
General Data Transmission
t0
Rising DCLK to CS
15
-
ns
t1
Chip select to positive edge of DCLK
15
-
ns
t2
Chip select to drive bus externally
-
-
ns
t3
Setup time command bit,
Data valid to positive edge of DCLK
30
-
ns
t4
Hold time command bit,
Data valid after positive edge of DCLK
30
ns
t5
Float time,
Positive edge of DCLK for last command
bit to bus float
30
DCLK/2
ns
t6
Bus driving time,
Positive edge of DCLK for last command
bit to bus drive
DCLK/2
+0
DCLK/2
+30
ns
t7
Setup time data bit,
Data valid to positive edge of DCLK
DCLK/2
+0
DCLK/2
+30
ns
t8
Hold time data bit,
Data valid after positive edge of DCLK
DCLK/2
+0
DCLK/2
+30
ns
t9
Hold time chip select,
Positive edge DCLK to negative edge of
chip select
30
ns
t10
Bus floating time,
Negative edge of chip select to float bus
030
ns
tTO
Timeout period in 2-wire mode (from
rising edge of DCLK)
17
27
µs
tCLK
Clock Timing
200
ns
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units



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