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AS5115

Datasheet - Detailed Descr i pti on

7 Detailed Description

The benefits of AS5115 are as follows:



Complete system-on-chip, no angle calibration required



Ideal for applications in harsh environments due to magnetic sensing principle



High reliability due to non-contact sensing



Robust system, tolerant to horizontal misalignment, temperature variations and external magnetic fields

7.1 Sleep Mode

The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode.

Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered

down with respect to fast wake up time.

7.2 SSI Interface

The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The

synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is

done in a way that the digital clock frequency can vary in a wide range.

Table 8. SSI Interface Pin Description

Port

Symbol

Function

Chip select

CS

Indicates the start of a new access cycle to the device

CS = LO

 reset of the digital interface

DCLK

DCLK

Clock source for the communication over the digital interface

Bidirectional data input output

DIO

Command and data information over one single line

The first bit of the command defines a read or write access

Table 9. SSI Interface Parameter Description

Symbol

Parameter

Notes

Min

Typ

Max

Unit

f_DCLK

Clock frequency at normal operation

The nominal value for the clock frequency can

be derived from a 10MHz oscillator source.

no limit

5

6

MHz

f_EZ_RW

Clock frequency at easy zap read

write access

no limit

5

6

kHz

f_EZ_PROG Clock frequency at easy zap access

program OTP

Correct access to the programmable zener

diode block needs a strict timing – the zap

pulse is exact one period.

The nominal value for the clock frequency can

be derived from a 10MHz oscillator source.

200

-

650

kHz

f_EZ_ARB

Clock frequency at easy zap analog

readback

20pF external load allowed.

The nominal value for the clock frequency can

be derived from a 10MHz oscillator source.

no limit

156.3

162.5

kHz

Parameter

Notes

Interface General at normal mode

Protocol: 5 command bit + 16 data input output

Command

5-bit command: cmd<4:0>

 bit<21:16>

Data

16-bit data: data<15:0>

 bit<15:0>

Interface General at extended mode

Protocol: 5 command bit + 46 data input output