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MSC1202Y2RHHT bảng dữ liệu(PDF) 73 Page - Texas Instruments

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tên linh kiện MSC1202Y2RHHT
Giải thích chi tiết về linh kiện  Precision Analog -to-Digital Converter
PDF  92 Pages
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Trang chủ  http://www.ti.com
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MSC1202Y2RHHT bảng dữ liệu(HTML) 73 Page - Texas Instruments

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MSC1200
MSC1201
MSC1202
SBAS317E − APRIL 2004 − REVISED MAY 2006
www.ti.com
73
Summation/Shifter Control (SSCON)
7
6
5
4
3
2
1
0
Reset Value
SFR E1h
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
00h
The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register, the 32-bit
SUMR3−0 registers will be cleared. The Summation registers will do sign-extend if Bipolar Mode is selected in ADCON1.
SSCON1−0 Summation/Shift Count.
bits 7−6
SSCON1
SSCON0
SCNT2
SCNT1
SCNT0
SHF2
SHF1
SHF0
DESCRIPTION
0
0
0
0
0
0
0
0
Clear Summation Register
0
0
0
1
0
0
0
0
CPU Summation on Write to SUMR0 (sum count/shift ignored)
0
0
1
0
0
0
0
0
CPU Subtraction on Write to SUMR0 (sum count/shift ignored)
1
0
x
x
x
Note (1)
Note (1)
Note (1)
CPU Shift only
0
1
Note (1)
Note (1)
Note (1)
x
x
x
ADC Summation only
1
1
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
ADC Summation completes, then shift completes
(1) Refer to register bit definition.
SCNT2−0
Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the
bits 5−3
SUMR0 register clears the interrupt.
SCNT2
SCNT1
SCNT0
SUMMATION COUNT
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
256
SHF2−0
Shift Count.
bits 2−0
SHF2
SHF1
SHF0
SHIFT
DIVIDE
0
0
0
1
2
0
0
1
2
4
0
1
0
3
8
0
1
1
4
16
1
0
0
5
32
1
0
1
6
64
1
1
0
7
128
1
1
1
8
256



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