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A

A

S

0

1

0

0

A1

A2

A0

0

Start

Condition

ACK

From Slave

ACK

From Slave

Data to Port 0

Data to Port 1

Slave Address (PCF8575)

R/W

P07 P06

1

P00

P17

P10 A

Integral Multiples of Two Bytes

P05

SCL

SDA

Write to

Port

Data Output

Voltage

P05 Output

Voltage

P05 Pullup

Output

Current

INT

ACK

From Slave

Data A0

and B0

Valid

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

A

A

S

0

1

0

0

A1

A2

A0

1

ACK

From Slave

ACK

From Master

R/W

P07 P06

P00

P17

ACK

From Master

SCL

SDA

Read From

Port

Data Into

Port

INT

P05 P04 P03 P02 P01

A

P10

P17 to P10

P07 to P00

P07 to P00

P17 to P10

A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by

a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.

P16 P15 P14 P13 P12 P11

P07 P06

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

PCF8575

WITH INTERRUPT OUTPUT

SCPS121D – JANUARY 2005 – REVISED APRIL 2007

Figure 4 and Figure 5 show the address and timing diagrams for the write and read modes, respectively.

Figure 4. Write Mode (Output)

Figure 5. Read Mode (Input)

7

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