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AS3931 bảng dữ liệu(PDF) 16 Page - ams AG

tên linh kiện AS3931
Giải thích chi tiết về linh kiện  3D Low Power Wakeup Receiver
PDF  31 Pages
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nhà sản xuất  AMSCO [ams AG]
Trang chủ  http://www.ams.com
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AS3931 bảng dữ liệu(HTML) 16 Page - ams AG

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www.austriamicrosystems.com/AS3931
Revision 6.2
15 - 30
AS3931
Datasheet - Detailed Descr i pti on
8.3 Basic Operation
8.3.1 LF Transmission Protocol
8.3.1.1 Data Pattern
The AS3931 identifies a 16 half-bit binary coded data pattern, which is ASK-modulated on a LF carrier. The pattern must contain 8 LOGIC 0 half-
bits and 8 LOGIC 1 half-bits in order to be DC free. Furthermore, for a proper detector threshold adaptation it has to be ensured that there are no
long groups of LOGIC 0 and LOGIC 1 half-bits. Therefore coding of the 16 half-bit binary data to 8 Manchester bits is common. This means that
8 consecutive half-bit pairs are grouped to Manchester bits whereas a Manchester bit 1 is a HIGH to LOW transition and a Manchester bit 0 is a
LOW to HIGH transition. The AS3931 supports the Manchester bit pattern 96 [hex] which in binary code is: 10 01 01 10 01 10 10 01. MSB is
transmitted first. The Manchester bit pattern i.e. the binary DATA pattern can be changed on demand by a metal mask modification.
8.3.1.2 Double Data Pattern
To increase the immunity against parasitic wakeups, the data pattern necessary for a successful wakeup can be doubled by programming the
AS3931: if the double data pattern is used, the pattern 96 has to be sent twice; after recognition of the first data pattern, the second data pattern
has to be sent immediately after the first one, otherwise no WAKE signal is generated. For the timing see Wake Up Frame on page 15. Setting
the bit M1 to 1 can program the double data pattern feature.
8.3.1.3 Wake Up Frame
The Wake Up Frame of AS3931 consists of a preamble used for detector threshold adaptation followed by the DATA pattern once (normal or
single Wake Up) or twice (double Wake Up) to be identified. We recommend a transmission protocol as shown on Figure 15 and Figure 16. The
preamble consists of a half-bit pattern 1010... with a specified number NPRE of half-bits (NPRE must be an even number in order to get complete
1/0 pairs). NPRE depends on the application and has influence on the wakeup and overload sensitivity. We recommend a minimum of NPRE = 8
half-bits (according to 4 manchester bits “1”).
Figure 15. Wake Up Frame of AS3931 with Single WAKE Data Pattern
Figure 16. Wake Up Frame of AS3931 with Double WAKE Data Pattern
Preamble
NPRE half- bits
Data 96
5.86 ms (16 half-bits)
WAKE
LF Carrier
Amplitude
Preamble
N
PRE half-bits
Data 96
5.86 ms (16 half
-bits)
WAKE
LF Carrier
Amplitude
Data 96
5.86 ms (16 half-bits)



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