AS3910 datasheet(41/77 Pages) AMSCO

41 / 77 page

ams Datasheet, Confidential: 2013-Oct [3-02]

AS3909/AS3910 – 41

Appl icatio n I n f o rm a t i o n

Interrupt Register and Associated Registers

Figure 29:

Mask Interrupt Register

Note: Default setting is set at power up and after Set Default command.

Figure 30:

Interrupt Register

Address # 07: Mask Interrupt Register

Type: RW

Bit

Name

Def.

Function

Comments

M_osc

mask INTR when oscillator frequency is stable

M_nfc

mask INTR due to nfc event

M_wl

mask INTR due to FIFO water level

M_rxs

mask INTR due to end of receive

M_txe

mask INTR due to end of transmission

M_err

mask INTR due to error in receive data coding

M_crc

mask INTR due to CRC error

M_col

mask INTR due to bit collision

Address # 08: Interrupt Register

Type: R

Bit

Name

Function

Comments

7I_osc

INTR when oscillator frequency is

stable

Set after enable

I_nfc

INTR due to nfc event

Set when nfc_t is 1 and en=0 informing that

an RF field has been detected,

Set when transmission could not be done

due to detection of RF field during RF

Collision Avoidance

I_wl

INTR due to FIFO water level

Set during receive, informing that FIFO is

almost full and has to be read out.

Set during transmit, informing that FIFO is

almost empty and that additional data has

to be sent.

4I_rxs

INTR due to end of receive

I_txe

INTR due to end of transmission

2I_err

INTR due to error in receive data

coding

This includes parity error and framing error

I_crc

INTR due to CRC error

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