AS3676 datasheet(81/92 Pages) AMSCO

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AS3676

Datasheet - D e ta i l e d D e s c r i p t i o n

Figure 40. Serial Interface Current Address Read

To keep the access time as small as possible, this format allows a read access without the word address transfer in

advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read

address.

Analogous to Random Read, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st register

byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes must

be responded to with an ACKNOWLEDGE from the master.

For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a sub-

sequent STOP condition.

8.12 Operating Modes

If the voltages on CLK and DATA is less than VPOR_PERI for > tPOR_DEB (see Table 115 on page 75), the AS3676 is in

shutdown mode and its current consumption is minimized (IBAT = ISHUTDOWN) and all internal registers are reset to their

default values.

If the voltage at CLK or DATA rises above VPOR_PERI, the AS3676 serial interface is enabled and the AS3676 and the

standby mode is selected. The AS3676 is switched automatically from standby mode (IBAT = ISTANBY) into normal

mode (IBAT = IACTIVE) and back, if one of the following blocks are activated:



Charge pump



Step up regulator



Any current sink



ADC conversion started



PWM active



Pattern mode active.

If any of these blocks are already switched on the internal oscillator is running and a write instruction to the registers is

directly evaluated within 1 internal CLK cycle (typ. 1µs)

If all these blocks are disabled, a write instruction to enable these blocks is delayed by 64 CLK cycles (oscillator will

startup, within max 200µs).

data 1

data 2

…

data n

N P

Read Register

WA++

Read Register

WA++

Read Register

WA++

Read Register

WA++

AS3675 (= slave) receives data

AS3675 (= slave) transmits data

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