AS3658F-BCTP datasheet(92/158 Pages) AMSCO

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AS3658

Data Sheet Confidential - Detail ed Descri ption- Audio Functi ons

9.4

ADC, DAC and Digital Audio Input

9.4.1 General

Digital audio data can be fed into the AS3658 via the I2S interface This input data is used by the 18-bit DAC to

generate the analog audio signal.

The stage is set to mute by default; If the DAC input is not enabled.

9.4.2 Signal Description

The digital audio interface uses the standard I2S format:

Left justified

MSB first

One additional leading bit

MCLK has to have a fixed ratio of 128 or 256 to LRCLK. With a LRCLK equal to 16, 32, 44.1 or 48kHz, the MCLK can

be generated by the on-chip PLL (do not use the internal PLL if there is jitter on the LRCLK1 or 2). For lower sample

rates the bit pll_mode has to be set (for sample rates between 8kHz and 12kHz).

The high going edge of MCLK has to have timing separation from LRCLK edges. If the clock generation is so that

LRCLK edges are at the same time as MCLK high going edges, the MCLK can be inverted to guarantee a proper DAC

function.

This audio input interfaces uses an I2S synchronizer to be able to handle audio sample length of 24bits or less.

5,4

ibr_hph<1:0>

R/W

Bias current reduction settings for headphone output

17%

34%

50%

I2S_select

R/W

Select I2S_1 input

Select I2S_2 input

I2S_mclk_en

R/W

Generation of the master clock by the internal PLL

Use Pin MCLK_1, MCLK_2 as masterclock input

Table 90. AudioSet2Register

Addr:75

Audio Set2

These bits control the Audio functions

Bit

Bit Name

Default Access

Description

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