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AS3675 bảng dữ liệu(PDF) 40 Page - ams AG |
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AS3675 bảng dữ liệu(HTML) 40 Page - ams AG |
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40 / 81 page ![]() www.austriamicrosystems.com/AS3675 1v3 39 - 80 AS3675 Datasheet - D e ta i l e d D e s c r i p t i o n 8.4.6 PWM Generator 6 pattern_slow 0R/W Pattern timing control 0b normal mode 1b slow mode (all pattern times are increased by a factor of eight) Table 54. Pattern End Register Addr: 54h Pattern End Bit Bit Name Default Access Description 0 pattern_end 0R pattern_end is toggled from 0 to 1 (or from 1 to 0) at each end of the pattern just before restarting of the internal pattern generator at the first bit of the pattern data (can be used to synchronize the baseband software to the pattern generator) 1 1. pattern_end toggles whenever the AS3675 is in active mode (see Section 8.12 Operating Modes on page 71) even if no pattern data has been setup. Table 55. LED Pattern timing pattern_slow pattern_delay2 pattern_delay[1..0] bit duration [ms] delay [s] between patterns pattern duration [s] (total cycle time: pattern + delay) delay between patterns pattern_color=0 pattern_color=1 0 0 00 31 100 0 1 1 0 0 01 31 100 1 2 0 0 10 31 100 2 3 00 11 31100 3 4 0 1 00 31 100 4 5 0 1 01 31 100 5 6 0 1 10 31 100 6 7 01 11 31100 7 8 1 0 00 250 800 0 8 1 0 01 250 800 8 16 1 0 10 250 800 16 24 1 0 11 250 800 24 32 1 1 00 250 800 32 40 1 1 01 250 800 40 48 1 1 10 250 800 48 56 1 1 11 250 800 56 64 1. Even by setting 000 for pattern delay, there is a small delay before the new patterns starts. Table 53. gpio current Register (Continued) Addr: 2Ch gpio current Bit Bit Name Default Access Description |
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