PIC16F84A datasheet(87/337 Pages) MICROCHIP

87 / 337 page

DS30234D-page 87

PIC16C6X

To enable the serial port, SSP enable bit SSPEN

(SSPCON<5>) must be set. To reset or reconﬁgure SPI

mode, clear enable bit SSPEN, re-initialize SSPCON

ures the SDI, SDO, SCK, and SS pins as serial port

pins. For the pins to behave as the serial port function,

they must have their data direction bits (in the TRIS reg-

ister) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS must have TRISA<5> set (if implemented)

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value. An example

would be in master mode where you are only sending

data (to a display driver), then both SDI and SS could

be used as general purpose outputs by clearing their

corresponding TRIS register bits.

Figure 11-4 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2) is to broadcast data by

the software protocol.

In master mode the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SCK output could be disabled

(programmed as an input). The SSPSR register will

continue to shift in the signal present on the SDI pin at

the programmed clock rate. As each byte is received, it

will be loaded into the SSPBUF register as if a normal

received byte (interrupts and status bits appropriately

set). This could be useful in receiver applications as a

“line activity monitor” mode.

In slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched interrupt ﬂag bit SSPIF (PIR1<3>) is

set.

The clock polarity is selected by appropriately program-

ming bit CKP (SSPCON<4>). This then would give

waveforms for SPI communication as shown in

Figure 11-5 and Figure 11-6 where the MSB is trans-

mitted ﬁrst. In master mode, the SPI clock rate (bit rate)

is user programmable to be one of the following:

• Fosc/4 (or TCY)

• Fosc/16 (or 4

• TCY)

• Fosc/64 (or 16

• TCY)

• Timer2 output/2

This allows a maximum bit clock frequency (at 20 MHz)

of 5 MHz. When in slave mode the external clock must

meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data

and wake the device from sleep.

FIGURE 11-4: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF register)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF register)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

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